DSP Basics
Digital signal processing (DSP) is what makes a modern transceiver dramatically better than an analog equivalent of the same cost. A DSP chip applies mathematical operations to streams of numbers (the digitized signal) to filter, demodulate, cancel noise, and decode digital modes. Tasks that once required precision analog components — crystal filters, balanced modulators, phase-shift networks — are now implemented as a few hundred lines of C or a few hundred multiply-accumulate operations per sample in a dedicated DSP chip or FPGA.
A typical DSP receive chain. The ADC digitizes the signal at a high sample rate; subsequent stages decimate the sample rate down to the audio band while performing frequency translation, filtering, and demodulation — all in software.
View LargerThe DSP Processing Chain
A receiver DSP chain follows a standard sequence: the ADC samples the signal at a high rate, a digital anti-alias filter removes out-of-band noise, a digital mixer (NCO) shifts the desired signal to baseband, a low-pass FIR filter selects the desired signal bandwidth and rejects all others, a decimation stage reduces the sample rate to match the output bandwidth, and a demodulator extracts the audio or data. Each of these steps is performed by arithmetic on arrays of numbers.
The key insight is that digital processing can be reconfigured in software: changing the filter bandwidth, the demodulation mode, the decimation ratio, or the noise reduction algorithm requires only a software update, not new hardware. This is why SDR radios — which expose the entire DSP chain to the user's software — are so popular for experimentation.
Convolution and Filtering
In DSP, filtering is implemented as convolution: multiplying each incoming sample by a set of coefficients (called the filter's impulse response) and summing the results. The filter coefficients determine the filter's frequency response. A low-pass filter has coefficients shaped like a sinc function; a band-pass filter has coefficients shaped like a windowed sinusoid. The filter output at each sample time is a weighted sum of the current and past input samples:
y[n] = ∑k=0N-1 h[k] × x[n-k]
Where y[n] is the filter output at sample n, x[n-k] is the input sample k steps in the past, h[k] is the kth filter coefficient, and N is the number of taps (filter length). Each output sample requires N multiply-accumulate operations.
The number of coefficients (taps) determines the filter's sharpness. A 128-tap FIR filter can achieve very steep roll-off and flat passband — performance impossible to match with a practical analog filter. The price is computation: 128 multiply-accumulate operations for every output sample. At 48 kHz audio sample rate, a 128-tap filter requires 6.1 million multiply-accumulates per second — trivial for a modern DSP chip but significant for a microcontroller.
Multiply-Accumulate Hardware
DSP chips and FPGAs contain dedicated multiply-accumulate (MAC) units — hardware blocks that compute (A × B) + C in a single clock cycle. A typical DSP chip might contain 16 parallel MAC units, each operating at 200 MHz, giving 3.2 billion MACs per second. This dedicated hardware is what makes FIR filtering and FFT computation practical in real time.
Modern microcontrollers such as the ARM Cortex-M4 and M7 include a floating-point unit with SIMD (single instruction, multiple data) MAC instructions, allowing ham radio DSP applications to run on low-cost embedded processors. GNU Radio and SDR software like WSJT-X use the host computer's CPU with SSE/AVX SIMD instructions to perform the same function.
Decimation and Interpolation
Decimation reduces the sample rate by an integer factor M. Every M-th sample is kept; the others are discarded. Before discarding samples, a low-pass filter must be applied to prevent aliasing (the Nyquist rule applies at the new lower sample rate). The filter and decimation together are called a decimation filter. Decimation reduces the computational load on subsequent processing stages — a 10× decimation filter reduces a 480 kHz sample stream to 48 kHz before the audio demodulator, so the demodulator runs at 1/10th the computational cost.
Interpolation increases the sample rate by inserting new samples between existing ones (upsampling) and then low-pass filtering to remove images. Interpolation is used in DAC output paths and SDR transmitters to increase the sample rate up to the DAC's operating rate. A two-stage interpolation of 10× followed by another 10× achieves 100× upsampling more efficiently than a single 100× stage.
CORDIC and Frequency Translation
Frequency translation (mixing) requires computing sine and cosine of the local oscillator frequency. In DSP, this is done with a Numerically Controlled Oscillator (NCO) — a counter that accumulates phase at a programmable rate and outputs sin/cos values. The sine and cosine outputs come from a lookup table or a CORDIC algorithm.
CORDIC (Coordinate Rotation Digital Computer) computes sin, cos, arctan, and related functions using only additions and bit shifts — no multipliers required. This makes CORDIC ideal for FPGAs and early DSP chips without hardware multipliers. The NCO generates two outputs (I and Q — in-phase and quadrature) that form a complex local oscillator. The incoming digitized signal is multiplied by the complex NCO output to shift the desired frequency to DC (baseband). This is the digital equivalent of the mixer stage in an analog superhet receiver.
DSP in Transceivers
IF filtering. The DSP chip in a modern HF radio implements the IF filter digitally. Instead of fixed-bandwidth crystal or mechanical filters, the user can select any receive bandwidth from 50 Hz to 10 kHz in 10 Hz steps by changing the FIR filter coefficients. The filter shape (Butterworth, Chebyshev, brick-wall, Gaussian) is also selectable from a menu. No analog radio can match this flexibility.
Noise reduction. DSP noise reduction algorithms analyze the received audio spectrum in real time and reduce components whose amplitude is varying rapidly (noise) while preserving components with stable amplitude (voice or CW). The ICOM IC-7300 implements spectral subtraction noise reduction using a short-time FFT analysis of the audio stream.
Automatic notch filter. Carrier interference from a heterodyne (two carriers close in frequency) produces a tone in the audio. The DSP auto-notch algorithm detects the tone frequency and places a narrow notch filter at exactly that frequency, attenuating the interfering tone without affecting the desired signal. A standard feature on modern transceivers, it would require a complex self-tuning analog circuit to achieve otherwise.
Digital mode encoding/decoding. Modes like FT8, WSPR, PSK31, and RTTY are entirely decoded by DSP software running on the host computer. The transceiver ADC digitizes the audio; software on the PC applies a DSP chain (bandpass filter, synchronizer, demodulator, decoder) to recover the digital data. This is why new digital modes can be deployed without hardware changes — they exist purely as DSP algorithms.
Frequently Asked Questions
What is the difference between a DSP chip and an FPGA for radio processing?
A DSP chip executes a sequential stream of instructions using dedicated MAC hardware — easy to program in C but limited in parallelism. An FPGA implements the processing pipeline as actual hardware logic running in parallel — much faster for tasks like FFT or FIR filtering, but harder to program (requires hardware description language like VHDL or Verilog). High-performance SDRs (Ettus USRP, LimeSDR) use FPGAs for the initial high-sample-rate processing and a CPU or DSP for the final demodulation. Entry-level SDR dongles push all processing to the host CPU.
How does DSP reduce phase noise in a transceiver?
DSP itself does not reduce phase noise — phase noise is generated by the local oscillator and is part of the analog RF chain before the ADC. What DSP can do is implement narrow digital filters that reduce the noise bandwidth, which reduces the effect of broadband phase noise on received weak signals. Very narrow CW filters (50 Hz) made practical by DSP do reduce the impact of reciprocal mixing compared to a wider analog filter, but the underlying phase noise of the oscillator is unchanged.
Test Your Knowledge
Answer the questions below to check your understanding. Every answer can be found in the lesson above.