Analog to Digital Conversion
Everything in the real world is analog. Sound waves, radio signals, voltages from sensors — they all vary continuously over a smooth, infinite range of values. But digital circuits work only with discrete numbers. The bridge between the analog world and the digital world is the analog-to-digital converter, or ADC. Every software-defined radio, every audio codec in a transceiver, and every digital signal processing system depends on ADCs to capture the outside world as binary numbers.
Understanding how ADCs work tells you why your SDR has a certain dynamic range, why a 24-bit audio ADC sounds better than a 16-bit one, what "12-bit ADC" means in the RTL-SDR dongle, and why you sometimes see distortion or spurious signals in your SDR software that were not present in the original RF signal.
A 4-bit ADC approximates the smooth input waveform as a staircase of 16 discrete levels. The difference between the true signal and the staircase is quantization error.
View LargerSampling: Taking Snapshots
An ADC measures the analog input signal at regular time intervals — this process is called sampling. Each measurement is called a sample. The rate at which samples are taken is the sample rate, measured in samples per second (S/s), kilosamples per second (kS/s), or megasamples per second (MS/s).
Think of sampling like taking photographs of a moving object. If you photograph it once per second, you get a snapshot of where it was at each second but know nothing about what it did between frames. If you photograph it 100 times per second, you have a much more detailed record. Similarly, a higher sample rate captures faster-changing signals more accurately.
The relationship between sample rate and the highest frequency that can be correctly captured is governed by the Nyquist theorem, covered fully in lesson M18I. For now, the key point is that the sample rate must be at least twice the highest frequency of interest. An audio ADC sampling at 44,100 S/s (the CD standard) can faithfully capture audio up to 22,050 Hz — well above the limit of human hearing (about 20 kHz).
Quantization: Assigning Numbers
After measuring the analog voltage, the ADC must represent it as a binary number. This process is called quantization. The full range of the input voltage (from 0 V to Vref, or from −Vref to +Vref for bipolar designs) is divided into 2N equal steps, where N is the number of bits. Each voltage range is assigned a binary code from 0 to 2N − 1.
The size of each step is called the least significant bit (LSB) voltage or the step size:
Step size = Vref / 2N
Where Vref is the full-scale input voltage range and N is the number of bits.
The minimum detectable voltage change is one step size. Signals smaller than one step are invisible to the ADC.
When the analog input voltage falls within a particular step's range, the ADC outputs the binary code for that step. This is an approximation — the ADC rounds the true voltage to the nearest available code. The rounding error, which is at most ±½ LSB, is called quantization error.
Resolution, Bit Depth, and Dynamic Range
The number of bits N directly determines three related quantities:
Resolution (number of steps): 2N. An 8-bit ADC has 256 levels. A 12-bit ADC has 4,096. A 16-bit ADC has 65,536. A 24-bit ADC has 16,777,216.
Dynamic range: the ratio between the largest and smallest signal the ADC can represent, expressed in dB. Each additional bit approximately doubles the number of levels and therefore adds about 6.02 dB of dynamic range:
8-bit ADC: 6.02 × 8 = 48.2 dB
12-bit ADC: 6.02 × 12 = 72.2 dB
16-bit ADC: 6.02 × 16 = 96.3 dB
24-bit ADC: 6.02 × 24 = 144.5 dB
This is why audiophiles prefer 24-bit recording over 16-bit: 48 dB more dynamic range means quieter noise floors and the ability to capture both very loud peaks and very quiet passages in the same recording without clipping or noise. Similarly, a 16-bit ADC in an SDR receiver has about 96 dB dynamic range — meaning it can simultaneously receive signals that differ by up to 96 dB in power level.
ADC Resolution Calculator
ADC Step Size and Dynamic Range Calculator
Enter the ADC reference voltage (full-scale input range) and bit depth. The voltage per step and theoretical dynamic range are calculated.
- N = 8 bits, Vref = 2 V (peak-to-peak)
- Step size = 2 V / 28 = 2 / 256 = 7.8 mV per step
- Minimum detectable signal: ~7.8 mV
- Dynamic range ≈ 6.02 × 8 = 48 dB
An 8-bit ADC is somewhat limited for radio work — modern SDRs use 12-bit or 14-bit ADCs for substantially better dynamic range.
Quantization Noise
The rounding error from quantization is not a single fixed error — it varies randomly as the input signal moves through the step boundaries. This random error looks like white noise added to the signal, called quantization noise. The magnitude of quantization noise is approximately:
Where dBFS means decibels relative to full scale. A 16-bit ADC has a quantization noise floor of approximately −(6.02×16 + 1.76) = −98.1 dBFS.
For a signal at full scale (0 dBFS), the SNR is approximately 98 dB. This places a hard floor on how quiet a signal the ADC can detect above its own noise. Improving ADC noise requires either more bits or oversampling (covered below).
ADC Architectures
There are several different circuit designs for converting an analog voltage to a binary number. Each has tradeoffs between speed, resolution, power, and cost:
Flash ADC
The fastest ADC type. A flash ADC uses 2N − 1 comparators in parallel, each comparing the input to a different reference voltage. All comparisons happen simultaneously, so the conversion is complete in one clock cycle. A 4-bit flash ADC needs 15 comparators; an 8-bit flash ADC needs 255. For high bit depths the number of comparators becomes impractical (a 12-bit flash ADC would need 4,095 comparators), so flash ADCs are typically limited to 6–8 bits but operate at speeds up to several gigasamples per second. Flash ADCs are used in oscilloscopes and high-speed RF sampling.
Successive Approximation Register (SAR) ADC
The workhorse of moderate-speed, moderate-resolution applications. A SAR ADC uses a single comparator and a DAC. It performs a binary search: first it tries the midpoint of the input range, compares input to that, then adjusts up or down by half the remaining range, and repeats N times. Each "guess" nails down one more bit. An N-bit SAR ADC requires N clock cycles per conversion. Typical SAR ADCs reach 12–18 bits at sample rates up to several MSPS. The analog-to-digital converter in most microcontrollers (including Arduino) is a SAR ADC.
Delta-Sigma (ΔΣ) ADC
The highest-resolution ADC type, capable of 20–32 bits. A delta-sigma ADC samples at a very high rate (oversampling, typically 64× to 512× the desired output rate) using a simple 1-bit ADC, then uses a digital filter and decimation process to produce high-resolution samples at a lower rate. The oversampling spreads quantization noise over a wider bandwidth, and the digital filter removes noise outside the signal band. Delta-sigma ADCs are used in audio recording equipment and in precision measurement instruments. The tradeoff is latency — the digital filter introduces delay proportional to the decimation ratio.
| Architecture | Speed | Resolution | Main use in radio |
|---|---|---|---|
| Flash | Very fast (>1 GSPS) | Low (6–8 bit) | Direct RF sampling oscilloscopes |
| SAR | Moderate (up to ~50 MSPS) | Medium (12–18 bit) | SDR front ends, microcontroller ADCs |
| Delta-Sigma | Slow to moderate (up to ~10 MSPS audio) | High (20–32 bit) | Audio codecs, precision measurement |
Oversampling
Oversampling means sampling faster than strictly required by the Nyquist criterion. If you sample at 4× the Nyquist rate instead of just 2×, the quantization noise is spread over twice the bandwidth. A filter that removes everything above the signal band then captures only the signal plus a fraction of the total noise. This improves the effective SNR by 3 dB for every doubling of the sample rate. Doubling the oversample ratio four times (a 16× oversampling factor) improves SNR by 6 dB — equivalent to one extra bit of resolution.
This is the principle behind delta-sigma ADCs: they use extreme oversampling (64× to 512×) to achieve very high effective resolution from a simple 1-bit core. It is also why modern SDRs benefit from higher sample rates even when you are listening to a narrow-band signal — the oversampling and digital filtering together reject more out-of-band noise and interference.
Practical ADC Specifications
When evaluating an ADC for radio work, the datasheet will include:
ENOB (Effective Number of Bits): the actual resolution in a real circuit, which is always less than the theoretical maximum due to noise and distortion. An ADC labeled "12 bits" might have an ENOB of only 10.5 bits under typical conditions.
SINAD (Signal-to-Noise and Distortion): the ratio of the signal power to the sum of all noise and harmonic distortion. ENOB = (SINAD − 1.76) / 6.02.
SFDR (Spurious Free Dynamic Range): the ratio between the signal and the strongest spurious component (usually a harmonic or intermodulation product). SFDR determines how close a strong signal can be to a weak one without the strong signal's spurs masking the weak signal. This is directly analogous to the third-order intercept point in analog RF systems.
ADCs in Ham Radio
The RTL-SDR uses the RTL2832U chip which contains an 8-bit ADC. Eight bits gives about 48 dB of theoretical dynamic range — adequate for general scanning but limited when a very strong nearby signal is present at the same time as a weak signal of interest. The strong signal's quantization spurs can raise the noise floor and mask the weak signal.
Higher-end SDR receivers like the Airspy HF+ Discovery use 18-bit delta-sigma ADCs specifically to achieve very high dynamic range (around 110 dB SFDR). This is why they handle strong broadcast signals much better than 8-bit dongles — the ADC can represent both the strong and weak signals without the quantization noise from the strong signal masking the weak one.
The audio ADC in your transceiver determines the dynamic range of the received audio chain. Modern HF transceivers use 24-bit delta-sigma audio ADCs which provide more than 100 dB of dynamic range — enough for both quiet QRP signals and loud pile-ups without clipping or noise floor problems.
Frequently Asked Questions
Why does my SDR show spurious signals that are not really there?
Spurious signals in SDR software often come from ADC non-linearity and quantization effects when a strong signal is present. When the ADC clips (the input exceeds Vref), or when its limited SFDR causes harmonic or intermodulation distortion, these products appear as real signals in the spectrum display. The solution is to reduce the RF gain to prevent clipping, use an attenuator in front of the SDR when receiving near strong signals, or upgrade to an SDR with better SFDR. An ADC cannot distinguish between a genuine signal and its own quantization artifact.
Does a higher sample rate ADC always sound better?
Not necessarily — the benefit of a higher sample rate is that you can capture higher frequencies and have more oversampling gain for noise reduction. But once the sample rate is well above twice the highest frequency of interest (as is the case for audio at 96 kHz or 192 kHz sample rates, where audible frequencies only go to 20 kHz), the extra samples provide no additional audible benefit. The bit depth (resolution) of the ADC is usually more important than sample rate for audio quality — a 24-bit/44.1 kHz recording is audibly superior to a 16-bit/192 kHz recording for most purposes.
What happens if the input voltage exceeds the ADC reference voltage?
The ADC clips — it outputs its maximum code (all 1s, or 2N−1) for any input above Vref, and its minimum code (all 0s) for any input below ground (or −Vref for bipolar designs). Clipping creates severe harmonic distortion with very high harmonic levels. In an SDR, overloading the ADC produces strong spurious signals across the entire spectrum. Always ensure the RF gain setting keeps the strongest signal below the ADC clipping point, typically leaving 6–10 dB of headroom.
Test Your Knowledge
Answer the questions below to check your understanding. Every answer can be found in the lesson above.