Counters and Shift Registers

Two of the most useful circuits you can build from flip-flops are counters and shift registers. Counters are fundamental to every frequency synthesizer in every radio ever made — they divide a high-frequency oscillator output down to a manageable reference frequency, and they count the timing intervals that define how long a CW dot or dash lasts. Shift registers move data in serial form, which is how digital modes send data from a processor to a modulator and how SPI and I²C communication buses operate inside your transceiver.

A 4-bit binary ripple counter. Each flip-flop divides its input frequency by 2. After four stages, the output frequency is one-sixteenth of the input clock.

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Binary Ripple Counter

A binary ripple counter is the simplest counter circuit, built by cascading T flip-flops where the Q output of each stage drives the clock input of the next. Each T flip-flop is configured to toggle on every clock edge (T input held HIGH). Because a T flip-flop toggles on every rising edge, it divides the frequency of its clock input by exactly 2 — the Q output changes once per two clock cycles.

The cascade works as follows: flip-flop Q0 receives the main clock and toggles at half the clock rate. Q1 is clocked by Q0's output, so it toggles at a quarter of the clock rate. Q2 toggles at one-eighth. Q3 at one-sixteenth. If you read Q3, Q2, Q1, Q0 together as a 4-bit binary number, you get a counter that counts from 0000 to 1111 (0 to 15) and then rolls over to 0000 again.

The term "ripple" describes the propagation delay: when the clock edge occurs, Q0 toggles first, then Q1 toggles a gate-delay later, then Q2 later still. The carry "ripples" through the stages. This creates a momentary glitch in the combined output as intermediate states pass through. For slow counter outputs this is unimportant, but for high-speed logic it can cause false decoding. Ripple counters are used in PLL frequency dividers, clock generators, and anywhere the individual stage outputs (at half-frequencies) are wanted.

Synchronous Counter

A synchronous counter clocks all flip-flops simultaneously from the same clock. Each flip-flop's J and K (or D) inputs are driven by combinational logic that determines whether that flip-flop should toggle on the next clock edge. Because all flops change at the same instant, there are no ripple glitches — all bits of the count update simultaneously.

The tradeoff is more complex control logic: each stage needs AND gates to check whether all lower-order stages are in the 1 state before it toggles. The 74HC163 is a popular synchronous 4-bit binary counter with parallel load, synchronous clear, and enable inputs. It can count up from 0 to 15 synchronously, be loaded with any preset value, or be held at any state — making it very flexible for divider chain design.

Modulo Counters

A binary N-bit counter counts modulo 2^N: it cycles through 2^N states. But you can build a counter that resets at any count, creating a modulo-M counter. A decade counter (modulo 10) is the most common example: it counts 0 through 9 and then resets to 0, just like one digit of a decimal odometer.

For a ripple counter, the technique is to use a NAND gate that monitors the specific count at which you want to reset, and feeds the output back to the asynchronous clear inputs of all flip-flops. When the counter reaches the target count, the NAND gate fires and immediately resets all flip-flops to 0. This creates a brief glitch at the reset count but is otherwise reliable for moderate speed applications.

Up/Down Counters

A basic counter counts up only. An up/down counter has a direction control input: when HIGH it counts up; when LOW it counts down. On each clock edge it either increments or decrements the stored count. Up/down counters appear in audio volume controls, menu navigation, and any application where the user can increment or decrement a value by pressing buttons.

The 74HC191 is a popular synchronous up/down 4-bit counter. It includes a parallel load input (to preset the count to any value), ripple clock output (for cascading multiple ICs), and a terminal count output (to indicate when the counter has reached its maximum or minimum). Cascading two 74HC191s gives an 8-bit up/down counter capable of representing 0 to 255.

Shift Registers

A shift register is a chain of D flip-flops where the Q output of each stage is connected to the D input of the next. On each clock edge, the data in each flip-flop shifts one position to the right (or left). New data enters at one end and exits at the other. Shift registers are used to convert between serial and parallel data formats, to delay data by a fixed number of clock cycles, and to implement serial communication interfaces.

To understand the shifting: if four D flip-flops are connected in a chain with the initial state 0000, and you apply the input sequence 1, 1, 0, 1 at the left end (one bit per clock edge), after four clock edges the register holds 1, 1, 0, 1 from left to right. The data has shifted through the register, one position per clock.

Shift Register Configurations

Shift registers are described by how data enters and exits:

The 74HC595 (SIPO) and 74HC165 (PISO) are common 8-bit shift register ICs that appear throughout Arduino projects, SDR accessories, and homebrew radio controllers. The 74HC595 lets a microcontroller drive 8 output lines using only 3 control pins by shifting data in serially and then latching it to the parallel outputs all at once.

Counters and Shift Registers in Ham Radio

PLL prescalers and dividers. Inside a phase-locked loop frequency synthesizer, the VCO output (say, 100 MHz) must be divided down to a reference frequency (say, 10 kHz) before being compared to the reference oscillator. This 10,000:1 division ratio requires a chain of divide-by-N counters. Older radios used chains of 74S163 or CD4040 ICs; modern designs integrate the divider into the PLL chip, but the underlying T flip-flop principle is identical.

Frequency counters. A digital frequency counter works by counting the number of clock cycles in a precise gate time (typically 0.1 s or 1.0 s). The gate time is generated by dividing a stable reference oscillator. The event count is accumulated in a binary counter. At the end of the gate time, the counter value is latched into a display register and the counter resets for the next measurement. Both the gate-time divider and the event counter are implementations of the circuits in this lesson.

Serial data interfaces. The Si5351 clock synthesizer used in many homebrew SDRs and transverters is programmed over an I²C bus. I²C is a 2-wire serial protocol that sends data one bit at a time. Inside the Si5351, shift registers capture the incoming serial configuration data and write it into the internal registers that control the frequency output. Similarly, SPI (Serial Peripheral Interface) buses in modern transceivers use PISO and SIPO shift registers to transfer data to DACs, display controllers, and RF switches.

DDS (Direct Digital Synthesis). In a DDS chip like the AD9851, the frequency control word is loaded via a serial or parallel interface into an internal phase accumulator register. The accumulator is a counter that increments by the frequency word on every reference clock cycle. The accumulator's most significant bits address a sine lookup table, which drives a DAC to produce the output frequency. The counter and shift register concepts tie directly into how DDS generates precise RF outputs.