Frequency Synthesizers

When you turn the VFO knob on a modern HF transceiver and hear each channel click into place — exactly 100 Hz apart, perfectly stable from the moment you select it — you are experiencing a frequency synthesizer at work. Before synthesizers became practical in the 1970s, amateur radios either used crystals (one crystal per frequency, limited channels) or variable-frequency oscillators (continuous tuning but prone to drift). The synthesizer ended both limitations at once: it delivers the stability of a crystal oscillator and the flexibility of a VFO, with the ability to tune to any frequency in a band with sub-hertz precision.

A frequency synthesizer is essentially a PLL-based circuit that translates a single stable reference frequency into any desired output frequency by controlling the parameters of the feedback loop. Understanding how this translation works — and understanding the compromises involved — is essential for anyone who wants to understand how modern radio equipment functions at a fundamental level.

Why Frequency Synthesis Was Revolutionary

Consider the situation facing an amateur radio operator in 1960. They wanted to work all 80 meters (3.5 to 4.0 MHz), 40 meters (7.0 to 7.3 MHz), and 20 meters (14.0 to 14.35 MHz) SSB. Their options were:

Crystal-controlled: Use a separate crystal for each frequency they wanted to use. At perhaps ten to twenty channels per band, this meant carrying dozens of crystals. Crystals cost money. The rig could only operate on pre-selected frequencies. Missing a rare DX station calling on a frequency you did not have a crystal for was a real operational limitation.

VFO-controlled: Use a single LC oscillator for each band, tunable across the entire band. This gave full frequency agility but required extreme mechanical and thermal stability to prevent drift — the bane of every homebuilder and many commercial designs. Warm-up drift, microphonics, supply sensitivity, and component aging all required constant countermeasures. A VFO used for CW with its narrow bandwidth required extraordinary stability that was difficult to achieve without exotic construction.

The frequency synthesizer resolved both problems. By locking a VCO to a crystal reference through a programmable PLL, engineers achieved the frequency agility of a VFO with stability approaching that of a crystal oscillator. The operator could tune to any frequency in the band in steps as fine as 1 Hz or 10 Hz, and each step was crystal-accurate. Modern rigs can achieve ±1 ppm frequency accuracy across the entire tuning range — essentially the accuracy of the 10 MHz reference crystal.

Integer-N Synthesis: The Foundation

Integer-N synthesizer architecture. The reference crystal is divided by R to set the comparison frequency (channel spacing). The VCO output is divided by programmable integer N and compared against the reference at the phase detector. When locked, f_VCO = N × (f_ref/R).

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The integer-N synthesizer is the direct application of the PLL principle described in the previous lesson, extended with a reference divider to make the channel spacing practical. It has two programmable dividers:

The R divider (reference divider) divides the crystal reference frequency down to the desired channel spacing frequency. If your crystal runs at 5.000 MHz and you want 5 kHz channel spacing, R = 5,000,000 / 5,000 = 1,000. The phase detector sees 5 kHz on both inputs when locked.

The N divider (feedback divider) divides the VCO output down to the same channel spacing frequency before feeding it back to the phase detector. When locked:

To tune to a different frequency, you change N. The PLL acquires lock at the new frequency, which takes from a few hundred microseconds to several milliseconds depending on the loop bandwidth. Modern microcontrollers can reprogram a synthesizer IC's N register via SPI or I²C bus in microseconds, making frequency changes nearly instantaneous from the operator's perspective.

Channel Spacing and Reference Frequency

The relationship between reference frequency and channel spacing is fixed by the integer-N architecture. The phase detector comparison frequency equals the channel spacing — and this creates a fundamental trade-off. Finer channel spacing requires a lower comparison frequency, which means:

• The N divider becomes larger (for HF synthesis with 1 Hz steps, N can be in the millions)
• The loop bandwidth must be kept narrow relative to the comparison frequency (typically loop bandwidth ≤ comparison frequency / 10 to prevent instability)
• A narrower loop bandwidth means slower lock time and less VCO noise suppression
• Reference spurs at the comparison frequency are closer to the carrier and harder to filter

This is why early PLL synthesizers typically offered 5 kHz or 10 kHz channel spacing — fine enough for AM and FM broadcasting or channelized amateur FM operation, but too coarse for SSB where operators need to tune in 100 Hz or even 10 Hz steps. Fine-step synthesis for SSB required either fractional-N techniques (developed in the 1980s) or offset techniques (discussed below).

The Frequency Offset Trick

Many transceiver designs solved the channel spacing problem by combining a coarse synthesizer with a fine-tuning VFO. The synthesizer provides the main frequency in, say, 10 kHz steps. A separate VFO (analog or digital) covers a span of ±10 kHz from the synthesizer frequency with fine, continuous resolution. The receiver or transmitter mixes the synthesizer output with the fine VFO output to produce any frequency within the band. This approach appears in many classic rigs from the 1970s and 1980s, including the Kenwood TS-520, Icom IC-260, and similar radios.

Prescalers and Dual-Modulus Division

At RF frequencies (say, 144 MHz), the N divider must count at 144 MHz / N_value per cycle. CMOS logic at that era could not count fast enough to directly implement a programmable N divider at UHF or microwave frequencies. The solution is a prescaler: a fast fixed-ratio divider (implemented in ECL or BiCMOS) that first divides the VCO output by a fixed number P to bring it down to a frequency manageable by slower logic. The slower programmable counter then divides by A or B, and the combination gives an effective divide ratio.

Dual-Modulus Prescaler

A dual-modulus prescaler can switch between two division ratios on command — typically P and P+1. Suppose P = 10. The prescaler normally divides by 10, but when commanded, it divides by 11. By combining this with two counters (an A counter and a B counter), the overall divide ratio N can be set to any integer from P (B−A) to P×B + A, covering all integers above a certain minimum. This makes a fully programmable synthesizer at high frequencies possible with only one fast divider stage.

The principle: count B cycles with the prescaler at ÷P/÷(P+1) mode. For the first A counts, use ÷(P+1). For the remaining B−A counts, use ÷P. Total counts at VCO frequency = A×(P+1) + (B−A)×P = AP + A + BP − AP = BP + A. So N = BP + A. With P = 8, A and B programmable independently, every integer N above 8 is achievable.

Modern synthesizer ICs have integrated the prescaler, A and B counters, and even the phase detector and charge pump into a single chip. The ADF4350 from Analog Devices, for example, covers 137.5 MHz to 4.4 GHz with a programmable divider and fractional-N capability, all in a 24-pin package.

Worked Example: 2-Meter FM Synthesizer

Fractional-N Synthesis: Finer Resolution

The integer-N architecture is limited: the channel spacing equals the comparison frequency, which means a 1 kHz comparison frequency is needed for 1 kHz steps. With a 1 kHz comparison frequency, N can be over 14,000 for HF, the loop bandwidth is forced below 100 Hz, reference spurs are very close to the carrier, and the PLL responds extremely slowly.

Fractional-N synthesis breaks the integer-N constraint by allowing the effective divide ratio to be a fraction. If the divider alternates between N and N+1 in a controlled pattern, the average divide ratio is N + k/M for some integers k and M. The output frequency is then:

Delta-Sigma Modulation and Noise Shaping

The simple fractional-N approach described above has a problem: the alternation between N and N+1 creates periodic phase disturbances at the phase detector at the fractional frequency. These appear as spurs on the output at offsets equal to the fractional frequency × comparison frequency. With k/M = 0.575, the pattern repeats with period 1/0.575 of the comparison frequency, producing a spur at about 5.75 kHz offset — potentially right in the receiver's passband.

The solution is delta-sigma modulation of the divide ratio. Instead of a simple periodic pattern, the delta-sigma modulator uses a feedback accumulator to create a pseudorandom sequence of divide ratios that achieves the correct average but whose spectral content is pushed to high frequencies (noise-shaped away from the carrier). The loop filter then suppresses this high-frequency noise.

A high-order delta-sigma modulator (third or fourth order) can shape virtually all the fractional noise above the loop bandwidth, leaving the output spectrum clean except for very close-in noise. This is why modern fractional-N synthesizers achieve low spurious outputs despite varying the divide ratio thousands of times per second. All modern synthesizer ICs — ADF4350/ADF4351 from Analog Devices, LMX2595 from Texas Instruments, Si4133 from Silicon Labs — use sigma-delta fractional-N architecture.

Synthesizer ICs: From Discrete to Integrated

The evolution from discrete PLL components to integrated synthesizer chips has been dramatic. In the late 1970s, building a PLL synthesizer required a handful of TTL or CMOS logic chips for the dividers, a separate PFD chip, a discrete charge pump, a loop filter, and a separate VCO. Today, a single small IC can provide the reference divider, PFD, charge pump, all programmable dividers, and even the VCO in one package.

The Si5351A deserves special mention. At under $3 in single quantities and using a simple I²C interface understandable to any Arduino user, it has become the go-to synthesizer IC for homebrewers. It provides three independent fractional-N synthesized outputs anywhere from below 1 MHz to 200 MHz — enough for an HF transceiver's LO, BFO, and calibration signal all from one chip. QRP Labs and many other homebrew kit suppliers use the Si5351A as the core frequency generation element.

Key Synthesizer Specifications

Synthesizers in a Complete Transceiver

A typical modern HF transceiver contains multiple synthesized signal sources working together. Understanding where each lives and what it does gives you a complete picture of the signal flow.

The VFO Synthesizer

The VFO synthesizer generates the local oscillator frequency that drives the first mixer in the receiver or modulates the exciter in the transmitter. When you tune the dial, you are reprogramming the N value in this synthesizer. For an HF transceiver with IF at, say, 9 MHz, receiving on 14.200 MHz requires a LO at 14.200 + 9 = 23.200 MHz (high-side injection) or 14.200 − 9 = 5.200 MHz (low-side injection). The synthesizer generates this LO frequency on demand.

The BFO/Carrier Insertion Oscillator

For SSB and CW reception, a second synthesized frequency (the beat frequency oscillator, BFO) is injected at the product detector after the IF filter. The BFO frequency is set to the IF ± the receiver's passband offset to place detected audio in the correct frequency range. Because USB and LSB require the BFO on opposite sides of the carrier, and CW reception requires a precise offset (usually 600–700 Hz), the BFO must be programmable — another synthesizer job.

The Calibration Oscillator

Many rigs include a calibration signal at a precise frequency — often a 1 MHz marker derived from the 10 MHz reference — that lets the operator zero-beat the receiver against a known-good frequency standard (WWV, WWVH, or CHU). In synthesized rigs, the accuracy of the calibration signal is only as good as the 10 MHz reference crystal, but that is usually more than adequate for amateur work.

Multiple Loop Architectures

Some high-performance transceivers use multiple PLL loops to achieve both fine resolution and excellent phase noise simultaneously. A common approach is the two-loop synthesizer:

Coarse loop: A high comparison frequency PLL (say, 100 kHz steps) generating the rough output frequency. Because the comparison frequency is high, the loop bandwidth can be wide, phase noise suppression is excellent, and reference spurs are far from the carrier.

Fine loop: A second PLL with a very low comparison frequency (say, 1 Hz) generates a small correction signal that is mixed with the coarse loop output to provide 1 Hz resolution. The fine loop VCO only needs to cover a small range (say, ±1 kHz), so its noise contribution is small.

The two outputs are mixed in a product detector, producing a sum or difference frequency at the desired operating frequency with the fine resolution of the second loop and the phase noise performance of the first. This architecture, while complex, appears in top-tier HF transceivers like the Elecraft K3 and the Icom IC-7600 series.

An alternative to multiple loops is the direct digital synthesis (DDS) approach, which generates any frequency digitally without a phase detector or lock time. DDS has its own trade-offs and is the subject of the next lesson.