Phase Locked Loops

A phase locked loop — the PLL — is one of the most elegant and powerful circuits in all of electronics. On the surface it appears complex: a loop of interconnected blocks that seem to chase each other in circles. In reality, the PLL solves a single problem with remarkable efficiency: how do you make a variable oscillator track a precise reference signal so accurately that the output inherits the reference's stability? The answer turns out to unlock an enormous range of applications — from FM demodulation in every analog receiver built in the last 50 years, to the frequency synthesizers that give modern transceivers their exact, rock-stable channel frequencies, to the clock recovery circuits inside digital data links. If you have ever wondered how your IC-7300 can tune to exactly 14.225.000 MHz and stay there without drifting, the PLL is a large part of the answer.

The Tuner Analogy: Chasing Phase

Imagine you are a musician trying to tune a guitar string to match a tuning fork. You strike the fork, listen to the reference pitch, then adjust the tuning peg until your string sounds the same. When the two pitches are identical, you hear no beating — the tones are in sync. If the string goes slightly sharp or flat, you correct it. The string's pitch always tries to match the fork.

A phase locked loop does exactly this, but electronically and at radio frequencies. The reference signal is the tuning fork — precise, stable, usually derived from a crystal oscillator. The voltage-controlled oscillator is the guitar string — tunable, but not inherently stable on its own. The phase detector plays the role of your ear, listening for any difference between the two. The loop filter is like the time it takes you to hear the difference and move the peg — it smooths out rapid corrections. And the feedback loop itself is what makes the whole thing work: the output is continuously fed back and compared against the reference so that any difference immediately generates a correction.

The key word is "phase," not just "frequency." When a PLL is locked, the output frequency is identical to the reference frequency. But more than that, the output phase has a fixed relationship to the reference phase. The PLL locks on phase, and equal phases imply equal frequencies. This is why a PLL output can be far more stable than the VCO alone — it borrows the precision of the crystal reference and imprints it onto the tunable oscillator.

The Four Essential PLL Blocks

The four essential blocks of a PLL: reference oscillator, phase detector, loop filter, and voltage-controlled oscillator, with the VCO output fed back to the phase detector to close the loop.

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Every PLL — whether inside an FM radio chip or a $5,000 synthesizer — contains these four essential blocks arranged in a loop.

1. Reference Oscillator

The reference oscillator provides the stable, accurate frequency that the loop will lock to. In virtually all practical PLLs, the reference is derived from a crystal oscillator. It might be a simple Pierce oscillator running at 10 MHz, or a temperature-compensated TCXO, or even a GPS-disciplined oscillator for laboratory-grade accuracy. Whatever its source, the reference must be more stable than what the VCO alone can achieve — that is the entire point. The PLL cannot generate accuracy out of nothing; it transfers the reference's accuracy to the VCO output.

In a frequency synthesizer, the reference is often divided down before reaching the phase detector. A 10 MHz crystal might be divided by 1,000 to produce a 10 kHz reference at the phase detector input, which then allows the PLL to tune in 10 kHz steps. The reference frequency at the phase detector sets the minimum tuning step size of the synthesizer.

2. Phase Detector

The phase detector (PD) — sometimes called a phase comparator — compares the phase of the reference signal with the phase of the signal fed back from the VCO output. It produces an output voltage proportional to the phase difference between the two inputs. When the loop is locked and the phase difference is constant (typically zero or a fixed offset), the phase detector output is a steady DC voltage. When there is a phase error — meaning the two inputs have different phases — the output voltage rises or falls to push the VCO back toward lock.

The phase detector is the heart of the feedback loop. It performs the comparison that drives all the corrective action. Without it, the loop is just a VCO with no reference — free-running and subject to all the drift problems covered in previous lessons.

3. Loop Filter

The phase detector output is not a smooth DC voltage; it contains components at the reference frequency and its harmonics in addition to the error signal. The loop filter removes these AC components and passes only the slowly-varying error information to the VCO. It is essentially a low-pass filter inserted in the feedback path.

The loop filter also sets the dynamic response of the PLL — how quickly the loop responds to changes and how stable it is. A wider filter bandwidth (higher cutoff frequency) makes the loop respond faster and lock in a shorter time, but it also passes more noise through to the VCO. A narrower filter makes the loop more stable and rejects more noise, but it responds slowly to changes. Every PLL designer must balance these competing demands based on the application.

4. Voltage-Controlled Oscillator (VCO)

The VCO generates the output signal. Its frequency is controlled by the DC tuning voltage from the loop filter: when the voltage rises, the frequency rises; when the voltage falls, the frequency falls. The VCO might be an LC oscillator with a varactor diode as the tuning element (most common in RF PLLs), a relaxation oscillator, or a ring oscillator depending on frequency range and application. In a PLL synthesizer, the VCO output is what drives the transmitter or provides the local oscillator signal in a receiver.

The VCO sensitivity, given the symbol K_VCO and measured in hertz per volt (Hz/V), describes how much frequency change the VCO produces for a given change in tuning voltage. A VCO with K_VCO = 1 MHz/V shifts its frequency by 1 MHz for every 1 V change in tuning voltage. This parameter critically affects loop dynamics.

How the PLL Achieves Lock: Step by Step

The locking process unfolds over several distinct stages. Understanding each stage will give you a solid mental model of what the loop is actually doing.

Stage 1: Free-Running State (Unlocked)

When power is first applied, the VCO runs at its free-running frequency — wherever it happens to land based on its component values and tuning voltage. This may be very different from the reference frequency. The phase detector sees two signals at different frequencies and produces an output that alternates rapidly between high and low voltage at a rate equal to the frequency difference. This alternating output passes through the loop filter and drives the VCO tuning voltage up and down.

Stage 2: Frequency Pulling

The loop filter is a low-pass filter, so it does not pass the rapid alternating phase detector output unchanged. It averages the output over time. If the VCO is running faster than the reference, the phase detector output produces a time-averaged error voltage that pushes the VCO tuning voltage down, slowing the VCO. If the VCO is running slower, the average error pushes the tuning voltage up. The VCO frequency is being pulled toward the reference.

Stage 3: Capture

As the VCO frequency approaches the reference frequency, the rate of phase detector output variation slows. The loop filter now passes a larger fraction of the error signal. The error becomes more effective at pulling the VCO. Eventually the VCO frequency comes close enough to the reference that the two signals slip in phase only slowly. The loop "captures" — it transitions from a frequency-difference tracking state into a phase-tracking state.

Stage 4: Lock

When locked, the output frequency exactly equals the reference frequency. The phase difference between reference and feedback is constant (possibly zero, possibly a small fixed offset depending on the phase detector type). The loop filter output is a steady DC voltage — the exact voltage needed to hold the VCO at that frequency. Any perturbation — temperature change, vibration, supply voltage fluctuation — that would normally shift the VCO frequency instead creates a small phase error, which the phase detector detects, which the loop filter passes to the VCO tuning input, which corrects the frequency back. The loop continuously self-corrects.

This self-correction is the fundamental advantage of a PLL. The VCO output borrows the long-term frequency accuracy of the crystal reference while retaining the short-term tunability of an LC or free-running oscillator.

Phase Detector Types

Two common phase detector types: the XOR (exclusive-OR) detector produces a pulse-width-modulated output proportional to phase difference over a ±90° range; the charge pump phase-frequency detector (PFD) uses UP/DOWN current pulses and can detect both phase and frequency errors over the full ±360° range.

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XOR Phase Detector

The simplest digital phase detector is an exclusive-OR (XOR) gate. It compares two digital square waves and produces an output that is high when the two inputs differ and low when they agree. If the two inputs are perfectly in phase (phase difference = 0°), the XOR output is always low. If they are 90° apart, the output is a square wave at 50% duty cycle. If they are 180° apart, the output is always high. The average DC value of the XOR output is proportional to phase difference over the range from 0° to 180°.

The XOR detector is simple and fast, but it has a limitation: it only detects phase difference, not frequency difference. If the two inputs are at very different frequencies, the XOR output alternates so rapidly that the loop filter cannot distinguish it from noise. The loop struggles to acquire lock when the frequency error is large. XOR detectors are best suited to applications where the VCO starts close to the target frequency.

Phase-Frequency Detector (PFD) with Charge Pump

The phase-frequency detector is the dominant choice in modern PLLs. Instead of comparing voltages directly, it uses flip-flop logic to detect which input leads the other in phase — and when the frequencies are different, which input is running faster. It produces separate UP and DOWN outputs that control a charge pump: a current source that pumps charge into the loop filter capacitor (UP) or drains charge from it (DOWN).

When the reference frequency is higher than the VCO output frequency, UP pulses are wider than DOWN pulses, so the charge pump net current flows into the capacitor, raising the VCO tuning voltage and speeding up the VCO. When the frequencies match but the VCO phase lags slightly, short UP pulses inject a small correction. When locked perfectly, both UP and DOWN produce identical narrow pulses that cancel, and the tuning voltage holds steady.

The PFD with charge pump has a linear range of ±360° (a full cycle), compared to the XOR detector's ±90°. More importantly, it can detect and correct frequency errors — not just phase errors — so it acquires lock reliably even when the VCO starts far from the reference frequency. This is why virtually all modern synthesizer ICs use the PFD + charge pump combination.

Phase Detector Comparison

The Voltage-Controlled Oscillator

The VCO in an RF PLL is usually an LC oscillator where a varactor diode serves as the tuning capacitor. As explained in earlier lessons, a varactor's junction capacitance changes with reverse bias voltage: more reverse bias means a smaller capacitor. By varying the voltage applied to the varactor, the tank circuit capacitance changes, and so does the oscillator frequency.

The VCO sensitivity K_VCO (also written K₀) quantifies this relationship:

A VCO with too large a K_VCO is very sensitive to supply noise and thermal drift — small disturbances produce large frequency excursions. A VCO with too small a K_VCO may not cover the required tuning range. Good PLL design requires matching the VCO gain to the loop requirements. When the loop is locked, the VCO tuning noise is suppressed by the loop gain, so PLLs with wider loop bandwidth can tolerate a noisier VCO.

The Loop Filter

The PLL loop filter acts as a low-pass filter within the feedback path. Below the loop bandwidth frequency, the VCO tracks the reference and reference phase noise appears on the output. Above loop bandwidth, VCO free-running phase noise dominates. The optimum loop bandwidth minimizes total output phase noise.

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The loop filter is usually a passive RC network (one or two poles) or an active filter built around an op-amp. Its two main functions are: remove the reference frequency ripple from the phase detector output, and set the loop's dynamic response.

Simple Passive RC Filter

The simplest loop filter is a single resistor and capacitor forming a first-order RC low-pass filter. The resistor is in series between the phase detector output and the capacitor, and the capacitor connects to ground. The loop filter capacitor is charged and discharged by the charge pump current, and the voltage across it drives the VCO. The RC time constant τ = R × C sets the loop bandwidth approximately as f_loop ≈ 1/(2πτ).

Second-Order Loop Filter

A single-pole filter gives a loop that can become unstable because the loop itself contributes phase shift. Most practical PLLs use a second-order loop filter — a capacitor in parallel with a series resistor-capacitor combination — which provides a "zero" (a frequency where phase shift is reduced) that stabilizes the loop. The addition of a second capacitor after the series RC provides extra attenuation of reference spurs without sacrificing stability.

Loop Bandwidth: The Critical Trade-Off

The loop bandwidth is the most important parameter of loop filter design. Inside the loop bandwidth, the VCO is phase-locked to the reference — it tracks the reference signal's phase noise and suppresses the VCO's own phase noise. Outside the loop bandwidth, the loop cannot follow fast perturbations, and the VCO's free-running phase noise appears on the output.

If the reference crystal has low phase noise (which crystals typically do) and the VCO has high phase noise (which free-running LC oscillators typically do), you want a wide loop bandwidth — let the reference suppress as much VCO noise as possible. But a wide loop bandwidth also passes reference frequency spurs to the output, creating unwanted sidebands. In a receiver, strong spurs create phantom signals on nearby frequencies. In a transmitter, spurs violate spectral purity requirements.

The optimum loop bandwidth sits at the crossover point where the reference phase noise equals the VCO phase noise — which typically falls somewhere between 1 kHz and 100 kHz depending on the oscillator types involved. This is a key design parameter that requires both analysis and empirical testing in practice.

PLL Parameters: Lock Range, Capture Range, Loop Bandwidth

Three frequency ranges describe a PLL's ability to lock and remain locked.

In general, hold range > capture range > loop bandwidth. A PLL can remain locked through a larger disturbance than it can acquire lock from a standing start. When designing a synthesizer, you ensure the capture range covers the full tuning range of the VCO so the loop can always acquire lock when frequency is changed.

Lock Time

Lock time is how long the PLL takes to settle to a new frequency after the reference or divider ratio changes. It is approximately 1/(loop bandwidth). A 10 kHz loop bandwidth gives a lock time of roughly 100 µs. A 100 kHz loop bandwidth gives 10 µs. In a transceiver that needs to hop frequencies, faster lock time allows quicker channel switching. Lock time and phase noise are again in direct conflict: wider bandwidth for faster lock time brings more noise.

Adding a Frequency Divider: Multiply the Reference

The simple four-block PLL described above locks the VCO output to exactly the same frequency as the reference. That is useful for locking an oscillator to a crystal standard, but it does not allow you to generate different output frequencies. The breakthrough comes from inserting a programmable frequency divider (divide-by-N counter) in the feedback path between the VCO output and the phase detector input.

This is the key insight behind frequency synthesis. The VCO output frequency is forced to be exactly N times the reference frequency. Change N, change the output frequency. The crystal reference never changes, so every output frequency benefits from crystal accuracy.

The minimum frequency step (channel spacing) equals the reference frequency at the phase detector. If you want 10 kHz channel spacing, you use a 10 kHz reference. If you want 1 kHz steps, you use a 1 kHz reference. Many synthesizers start with a higher-frequency crystal (say, 10 MHz) and divide it down to the desired reference frequency using a fixed prescaler.

Worked Example: 14 MHz HF PLL

PLL Applications in Ham Radio

FM Demodulation

One of the oldest and most elegant uses of a PLL is as an FM demodulator. In FM, the carrier frequency is varied (deviated) by the audio signal — higher audio peaks produce higher deviation. A PLL locked to the FM carrier tracks this deviation: as the carrier frequency rises and falls with the audio, the loop filter output voltage rises and falls to keep the VCO following the carrier. The loop filter output voltage is therefore a direct copy of the original audio modulation. This is the demodulated audio signal.

FM demodulation via PLL became practical with integrated circuit PLLs like the NE565, CA3089, and MC3357. These chips contain all four PLL blocks on a single die. The CD4046 CMOS PLL, popular in homebrew radio projects, is another well-known example. PLL-based FM demodulation replaced the discriminator and ratio detector circuits in most equipment from the late 1970s onward because the IC approach is smaller, cheaper, and requires no coil alignment.

Frequency Synthesis

The largest application of PLLs in amateur radio is frequency synthesis — generating any desired frequency from a single crystal reference. The receive VFO (local oscillator), the carrier insertion oscillator (BFO), the transmitter exciter frequency — all of these can be generated by PLLs in a modern rig. The next lesson covers frequency synthesis in detail.

Clock Recovery in Digital Modes

Digital modes such as PSK31, FT8, and WSPR use coherent demodulation that requires knowledge of the exact transmit clock frequency and phase. When receiving a digital signal, a PLL in the receiver locks to the incoming data transitions and recovers the clock embedded in the data stream. This recovered clock then gates the data slicer at exactly the right moments to correctly identify each bit. Without PLL-based clock recovery, coherent digital demodulation at low SNR would be impossible.

Reference Frequency Distribution

In a station with multiple pieces of equipment — transceiver, amplifier, SDR panadapter, computer sound card interface — it can be valuable to lock all equipment to a common 10 MHz reference. A PLL in each device locks its internal crystal to the 10 MHz reference, ensuring everything is frequency-coherent. GPS-disciplined oscillators (GPSDOs) that provide a 10 MHz output locked to GPS atomic timing are popular for this purpose among serious contesters and weak-signal operators.

Phase Noise in PLLs

A PLL does not produce a perfectly clean output signal. There are two sources of phase noise in a PLL output, and they dominate in different regions of the frequency spectrum:

Inside the loop bandwidth: The VCO is phase-locked to the reference, so the output phase noise closely follows the reference phase noise multiplied by N². When the divide ratio N is large — as it is in a high-frequency synthesizer — the reference noise is multiplied by 20 × log₁₀(N) dB. A synthesizer with N = 14,000 adds 20 × log₁₀(14,000) = 82.9 dB to the reference phase noise inside the loop bandwidth. This is why low-phase-noise references and small frequency steps are both important for clean synthesizer outputs.

Outside the loop bandwidth: The loop cannot suppress VCO noise at offsets beyond the loop bandwidth. The VCO's free-running phase noise appears directly on the output. This is why VCO quality matters — you need a high-Q tuned circuit (good inductor, stable capacitor) in the VCO to minimize its free-running phase noise.

Reference spurs: At offsets equal to the reference frequency and its harmonics, the output spectrum often shows discrete sidebands called reference spurs. These arise from charge pump leakage, substrate coupling in the IC, and other non-ideal behaviors. Reference spurs appear as discrete signals that create ghost interference in a receiver. Careful loop filter design and good PCB layout minimize them. A typical well-designed synthesizer achieves −80 to −100 dBc reference spurs. FCC Part 97 rules require amateur transmitters to have suppressed spurious emissions, so synthesizer spur performance is a real regulatory concern.

Experiment: Observing PLL Lock with a CD4046