Flip-Flops and Latches

Logic gates have no memory. Remove the input signal and the output immediately returns to whatever state the inputs dictate. For digital circuits to store information — to remember what happened, hold a frequency setting, or track the current state of a sequence — you need memory elements. The basic memory element in digital electronics is the flip-flop.

A flip-flop is a circuit that can be in one of two stable states and will remain in that state indefinitely until told to change. It stores exactly one bit. Chain many flip-flops together and you can store bytes, words, or entire data records. Organize flip-flops with feedback and you get counters, shift registers, and state machines — the building blocks of every digital system in your radio.

D flip-flop timing diagram. The Q output changes only on the rising edge of the clock. Setup time and hold time windows are shown around each clock edge.

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Why Digital Circuits Need Memory

Imagine trying to build a digital frequency counter without memory. The counter must count the number of clock cycles in a one-second window and display the result. But the display must remain stable while counting continues in the next window. Without memory elements to hold the previous count while the next one accumulates, the display would flash incomprehensible intermediate values.

Memory is needed everywhere in digital systems: to hold the current operating frequency while you change another setting; to remember which menu item was selected last; to store the incoming data bits of an FT8 frame while they are assembled into a complete message; to maintain the state of a CW keyer between paddle contacts. All of this storage, from a single status bit to a megabyte firmware image, is ultimately built from flip-flops.

The SR Latch

The simplest memory element is the SR latch (Set-Reset latch). It has two inputs — S (Set) and R (Reset) — and two outputs — Q and Q̄ (Q-bar, the complement of Q). A HIGH on S forces Q to 1 (sets the latch). A HIGH on R forces Q to 0 (resets the latch). When both S and R are LOW, the latch holds its previous state indefinitely.

The SR latch is built from two cross-coupled NOR gates (or two NAND gates for the active-low version). The cross-coupling is what creates the memory: the output of each gate is fed back to the input of the other, creating a stable feedback loop that maintains one of two states. The forbidden S=1, R=1 condition drives both outputs to the same value (either both 0 or both 1 depending on implementation), violating the requirement that Q and Q̄ are always complements.

A limitation of the SR latch is that it is level-sensitive — it responds to input levels continuously, not at a specific moment. This makes it difficult to use in synchronous digital systems where all changes should occur at the same clock edge.

The D Flip-Flop

The D flip-flop (Data or Delay flip-flop) is the most widely used flip-flop in practice. It has one data input D, a clock input CLK, and outputs Q and Q̄. On the active clock edge (typically the rising edge — the moment CLK goes from LOW to HIGH), the Q output takes on the value that was present at the D input just before the edge. After the clock edge, Q holds that value regardless of what D does, until the next clock edge.

The D flip-flop eliminates the forbidden state problem of the SR latch by having only one data input. Whatever is on D at the clock edge is what Q becomes. You can think of the D flip-flop as a "snapshot" circuit: on each clock edge, it photographs the D input and holds that photograph until the next edge.

D flip-flops are available in ICs such as the 74HC74 (dual D flip-flop with preset and clear). Each flip-flop in the 74HC74 also has active-low asynchronous preset (PRE̅) and clear (CLR̅) inputs — these override the clock and force Q HIGH or LOW immediately, regardless of the clock state.

The JK Flip-Flop

The JK flip-flop is an enhanced version of the SR latch that resolves the forbidden state. It has two inputs — J (equivalent to Set) and K (equivalent to Reset) — plus a clock input. Unlike the SR latch, the condition J=1, K=1 is not forbidden: instead, J=K=1 causes the flip-flop to toggle — its output reverses whatever state it was in.

The JK flip-flop is the most general-purpose flip-flop — any other flip-flop type can be implemented using a JK with appropriate input connections. In practice, D flip-flops are more common in modern digital design because synthesis tools handle them more efficiently, but JK flip-flops are still found in older radio equipment and in exam questions about digital logic.

The T Flip-Flop

The T flip-flop (Toggle flip-flop) is the simplest application of the JK: connect J and K together and you get a flip-flop with a single T input. When T=1 and a clock edge occurs, the output toggles. When T=0, the output holds. This makes the T flip-flop a natural frequency divider: the output changes state on every clock edge when T is held HIGH, so the Q output changes at exactly half the clock frequency.

A single T flip-flop divides the clock frequency by 2. Connect two T flip-flops in series (Q of first feeds CLK of second) and you divide by 4. Three in series divide by 8. This cascading of T flip-flops forms a binary ripple counter, which is covered in the next lesson.

Edge-Triggered vs Level-Triggered

The distinction between latches and flip-flops comes down to when they respond to their inputs:

Level-triggered (latch): The output follows the input continuously whenever the enable or clock input is at the active level. The SR latch is level-triggered — it responds to S and R continuously. This causes a problem called transparency: changes at the input "pass through" to the output while the enable is active, which can cause race conditions in synchronous systems.

Edge-triggered (flip-flop): The output only samples the input at the precise moment of a clock edge (rising or falling). Between clock edges, the input can change freely without affecting the output. This makes edge-triggered flip-flops the standard building block for synchronous digital design — all state changes happen at known, predictable clock edges.

Setup Time and Hold Time

For an edge-triggered flip-flop to reliably capture the correct data value, the D input must be stable for a minimum time before the clock edge (setup time, t_su) and for a minimum time after the clock edge (hold time, t_h). If the data changes within these windows, the flip-flop may enter a metastable state — an indeterminate output that is neither fully HIGH nor fully LOW and may take an unpredictable amount of time to resolve.

Typical setup and hold times for 74HC-series CMOS flip-flops are on the order of 5 to 20 ns. This is why clock frequency limits exist: at very high clock rates, there is not enough time for data to propagate through the combinational logic between flip-flops, violating setup time. Maximum clock frequency is therefore determined by the longest combinational path delay plus setup time in the circuit.

Flip-Flops in Ham Radio

Frequency dividers in PLLs. The phase-locked loop (PLL) synthesizers in virtually every modern transceiver use chains of T flip-flops (in ripple or programmable divide-by-N counter configurations) to divide the VCO frequency down to a reference frequency. A 28 MHz VCO output must be divided by some integer N before being compared to a 10 kHz reference — that division is performed by cascaded flip-flops in the feedback path of the PLL.

Operating mode and band memory registers. The current band, mode, power level, and filter bandwidth are stored in register circuits built from D flip-flops. When you press a memory recall button, the microcontroller loads data into these registers, and the flip-flops hold the settings until they are changed again. This is why settings are retained when you change bands and return — they are stored in latched registers throughout.

Digital mode demodulation. BPSK31 and other phase-shift keying modes use D flip-flops as part of the clock recovery circuit. The received signal's phase transitions are used to re-align a local clock, and flip-flops capture data bits synchronously with the recovered clock. Without clock recovery flip-flops, the data stream would be sampled at arbitrary times and the bit decisions would be unreliable.

Keyer iambic state machine. An iambic CW keyer must remember whether it is currently sending a dot, a dash, a pause, or nothing. This state information is stored in flip-flops. The paddle switch inputs set or reset latches that determine what element the keyer is currently generating. The specific sequence of elements depends not just on current paddle state but on what the keyer was doing one element ago — memory stored in flip-flops.